Thomas Roche: EUCLEAK
Abstract
Secure elements are small microcontrollers whose main purpose is to generate/store secrets and then execute cryptographic operations. They undergo the highest level of security evaluations that exists (Common Criteria) and are often considered inviolable, even in the worst-case attack scenarios. Hence, complex secure systems build their security upon them.
In this talk we will present a side-channel vulnerability in the cryptographic library of Infineon Technologies, one of the most important secure element manufacturers. This vulnerability – that went unnoticed for 14 years and about 80 highest-level Common Criteria certification evaluations – is due to a non constant-time modular inversion. The attack requires physical access to the secure element (few local electromagnetic side-channel acquisitions, i.e. few minutes, are enough) in order to extract an ECDSA secret key. The attack is performed on a FIDO hardware token from Yubico where it allows to create a clone of the FIDO device. Yubico acknowledged that all YubiKey 5 Series (with firmware version below 5.7) are impacted by the attack and in fact we show that all Infineon security microcontrollers (including TPMs) that run the Infineon cryptographic library are vulnerable to the attack.
Biography
Thomas Roche is co-founder and security expert at NinjaLab (ninjalab.io). His research interests lie in all aspects of cryptography with a focus on implementation issues. Thomas hobby these last years: trying to find side-channel vulnerabilities inside the most secure chips available on the market. After his PhD in applied mathematics from Grenoble University and a short postdoc at the university of Paris 8 and Oberthur Technologies (now IDEMIA), Thomas worked 4 years at ANSSI (French Cybersecurity Agency) and 2 years at APPLE prior to founding NinjaLab with Victor Lomné in 2017.
Makoto Nagata: Si Substrate Backside of ICs as Attack Surfaces and Countermeasures of Physical Security
Abstract
Si substrate backside of an integrated circuit (IC) chip, more precisely, the backside surface of its Silicon substrate, provides open areas for performance improvements as well as for adversarial security attacks. These are potentially contradictory or traded off in the design of IC chip toward the higher level of performance and security particularly along with advanced packaging technologies. An attacker leverages Si substrate backside to scan side channel leakages from and also to inject intentional faults to a crypto processor, through a variety of physical interactions with electromagnetic, electrical, thermal and luminescent medias. This talk overviews Si backside physical attacks and addresses the exploration of countermeasures by physical structures. The chip-backside vulnerability of an IC chip will be experimentally given with Si examples as well as analytically described with simulation models.
Biography
Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He is a full professor at Kobe University since 2009, and served for the dean of the graduate school of science, technology and innovation (2022-2023).
